1. Technical Field of the Invention
The present invention related generally to the domain of high resistivity silicon substrate, and more particularly, to an electronic component using this technology.
2. Description of Related Art
Silicon on insulator (SOI) is a layered structure created on an insulating substrate.
With regard to electronic components such as transistors, SOI differs from generic CMOS in that its silicon junction is above an electrical insulator.
The advantage is that this insulator reduces the capacitance, meaning a SOI transistor has less to charge-up before completing a switch, which results in reduced switching time and reduced switching energy over CMOS-based chips. Also, there is a reduction in transistor leakage current.
Such a process reduces the amount of electrical charge that a transistor has to move during a switching operation, thus increasing speed.
As an example, SOI can be used as an alternative to bulk silicon for the manufacturing of microwave transistors.
As known to those skilled in the art, a SOI is a layered structure, generally made of piled up layers of copper, in which the last layer of metallization, i.e. the most distant from the substrate, called a conductive layer, is used for the transport of current, i.e. electrically connected to a power supply source.
Intermediate layers, located between said substrate and said last metallization layer, are used, e.g. for protective or isolation purposes, or more generally not used.
Additionally to this set of metallization layers, power can be supplied to the last layer of metallization through a power supply layer, e.g. made of aluminum.
It is known to those skilled in the art that the distance between the substrate and the conductive last metallization layer must be over a given value, depending on the technology (65 nm, 130 nm, etc.) and other parameters.
For example, the electronic component may be a coplanar waveguide. A coplanar waveguide comprises a central ribbon connected to a power supply source, and two symmetrical ground ribbons connected to a ground potential and located on both sides of said central ribbon.
It is commonly accepted that the distance between the central ribbon and its adjacent ground ribbon depends on the distance (height) between the last layer of metallization and the substrate.
Said distance (height) is considered to be a constraint with regard to the evolution of techniques and customer needs which lead to the reduction of thickness of all components and layers. Said reduction increases risks of electrical losses in the substrate.
And is it commonly accepted that decreasing said distance (height) between the last layer of metallization and the substrate would lead to increase the parasitic capacitance between the transmission line and the substrate.